The present invention relates to power switching circuits, and in particular, to power MOSFET switching circuits, and more particularly, to circuits for protecting such power MOSFETs and their drivers from the effects of load dumps.
Load dumps are relatively slow voltage surges which occur on power supplies. In automotive applications, such load dumps may occur when the automotive storage battery becomes temporarily disconnected from the supply. In such instances, a slow voltage surge may occur on the supply voltage line which can damage the power switches and their driver circuits. For example, in a typical automotive application, which has a supply voltage of approximately 14 volts, a load dump of 3 to 6 times the normal supply voltage can occur.
FIG. 1 shows a typical prior art switching circuit. A power MOSFET switch 10 includes main current carrying cells 10A, a reverse polarized body zener diode 10B and current sense cells 10C that are part of the FET and are used to determine the current through the FET and for providing a feedback signal VFB. The current is determined across a sense resistor RS.
A gate drive signal on line 11 is provided to the gate of the power FET 10 which is coupled in series with the load 20, which might comprise, for example, a motor. The FET 10 and the motor 20 are coupled between the supply voltage VDD and power ground. A low side switch 12 may also be provided, driven by another gate drive signal out of phase with the gate drive signal on line 11 in some applications.
The circuit of FIG. 1 includes an active clamp comprising, in its simplest form, zener diode DZ, optionally diode D1 and optionally resistor RA. If the voltage VDD increases beyond the normal supply voltage, and if the voltage VDD increases beyond the avalanche voltage VZ of zener diode DZ, the gate voltage to FET 10 will be clamped at a voltage approximately VZ below VDD. This is shown graphically in FIG. 1A which shows the voltage VDD increasing beyond the clamp voltage of approximately 30 volts. When VDD increases beyond 30 volts, the output across the clamp (measured between VDD and the clamp output) is clamped to the clamp voltage of 30V.
FIG. 1B shows another implementation of the clamp circuit in which a transistor Q1 functioning as an emitter-follower is turned on when diode DZ avalanches. When transistor Q1 turns on when diode DZ conducts at its avalanche voltage, a voltage is produced across resistor RB clamping the gate of FET 10 at a voltage V clamp of approximately VZ plus the forward drops of diode D1 and VBE of transistor Q1.
Clamping of the gate voltage will prevent damage to the FET and its driver circuits in the event of a load dump.
The problem with this circuit is that the power MOSFET 10 may be overheated if Vout>Vz plus about 2 volts (due to load dump) and power switch 10 may be damaged. At voltages VDD between 35 volts and approximately 60 to 70 volts, the driver and switch are still adequately protected by this circuit. However, at VDD voltages above approximately 75 volts, the switch 10 may be damaged because the clamp circuit is incapable of providing adequate voltage protection to the gate of FET 10. To solve this problem, FETS and drivers having higher reverse voltage ratings are necessary using the prior art circuit or expensive zener diodes are disposed across the supply voltage.